1. Field of the Invention
This invention relates to a processing unit containing a DMA controller, and more particularly it relates to a processing unit containing a DMA controller wherein transfer of processor data and DMA data and processor address and DMA address is improved.
2. Description of the Background Art
FIG. 6 is a schematic block diagram of a processor containing a prior DMA controller. A processor 1 comprises a logic section 2, a DMA controller 3, an internal data memory 4 and an external interface circuit 5. The logic section 2, internal data memory 4 and external interface circuit 5 are connected together by a 2 n-bit processor data bus 6, a 2 n-bit DMA data bus 7, a 2 m-bit processor address bus 8 and a 2 m-bit DMA address bus 9, the DMA controller 3 being connected to the DMA address bus 9.
FIG. 7 is a more specific block diagram of the external interface circuit shown in FIG. 5. In FIG. 7, the processor data bus 6 is connected to a latch 51, the DMA data bus 7 is connected to a latch 52, the processor address bus 8 is connected to a latch 53 and the DMA address bus 9 is connected to a latch 54. The outputs of the latches 51 and 52 are connected to a multiplexer 55, which outputs data latched in the latch 51 or 52 to a data terminal 10. The outputs of the latches 53 and 54 are given to a multiplexer 56, which outputs an address latched in the latch 53 or 54 to an address terminal 11.
FIG. 8 is a diagram showing the transfer timing for concurrent operation in the external interface circuit shown in FIG. 7.
Referring to FIGS. 6 through 8, the transfer operation of data and address in a processor containing a conventional DMA controller will now be described. When concurrent operation of the processor 1 and the DMA controller 3 does not take place and the data from the processor data bus 6 is outputted, the data from the processor data bus 6 is latched in the latch 51, and the data latched in the latch 51 by the multiplexer 55 is selected and outputted to the data terminal 10. As in the case of data, an address from the processor address bus 8 is latched in the latch 53, selected by the multiplexer 56 and outputted to the address terminal 11.
On the other hand, when the concurrent operation of the processor 1 and the DMA controller 3 takes place, for example, supposing that the processor 1 is kept waiting, the data from the DMA data bus 7 is latched in the latch 52, selected by the multiplexer 55 and outputted to the data terminal 10. Similarly, the address from the DMA address bus 9 is latched in the latch 54, selected by the multiplexer 56 and outputted to the address terminal 11.
As described above, when the processor 1 and the DMA controller 3 concurrently operate, one transfer alone is performed while the other is kept waiting. For example, as shown in FIG. 8, in the case where transfer is performed such that the DMA controller 3 transfers data in the burst mode to continuously transfer m words, the processor 1 is kept waiting for at least m machine cycles, resulting in a decrease in transfer efficiency.